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500 mhz dual dcl adate206 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2008 analog devices, inc. all rights reserved. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. features driver, comparator, and active load 500 mhz toggle rate inhibit mode function dynamic clamps operating voltage range: ?1.5 v to 6.5 v output voltage swing: 200 mv to 8 v four range adjustable slew rate true/complement data mode bit 100-lead tqfp package, exposed pad low per channel power 1.4 w with load off 1.75 w with load programmed at 20 ma nominal low leakage (<10 na) in high-z mode driver 50 output resistance 1 ns minimum pulse width for a 3 v step load: ?35 ma to +35 ma maximum current range applications automatic test equipment semiconductor test systems board test systems instrumentation and characterization equipment general description the adate206 is a complete, single-chip solution that performs the pin electronics functions of driver, comparator, and active load (dcl) for ate applications. the active load can be powered down if not used. the driver is a proprietary design that features three active modes: data high mode, data low mode, and term mode, as well as an inhibit state. the driver has low leakage (<10 na) in high-z mode. the output voltage range is ?1.5 v to +6.5 v to accommodate a wide variety of test devices. the adate206 supports four programmable tr/tf times for applications where slower edge rates are required. the edge rate selection is done via two static digital cmos select bits. the input data to the driver can be inverted using a single cmos logic bit. this feature can be used for system calibration or applications where complement input data is needed. functional block diagram v cc (18, 19, 57, 58, 77, 78, 89, 98, 99) driver 1x comp_h iol ioh temp gndref vioh viol vcom cvl comp_l_n comp_h_n comp_h_p cvh lden vten dr_en_n dr_en_n_t dr_en_p_t dr_en_p dr_data_n dr_data_n_t dr_data_p_t dr_data_p dr_inv vih vil vit comp_l_p cllm dut clamph clampl temp sensor (5 diodes) logic load logic 7 69 8 68 9 67 6 70 81 95 88 11 66 10 65 22 54 23 53 24 52 25 51 26 50 27 49 28 48 29 47 15 61 14 62 4 72 3 73 2 74 31 45 91 85 32 44 13 63 comp_l 34 42 35 41 90 86 1 75 nc (30, 46) shields (80, 82, 94, 96) adate206 05738-001 vee (16, 17, 33, 43, 59, 60, 84, 87, 92) gnd (5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97,100) figure 1.
adate206 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 table of contents .............................................................................. 2 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................8 esd caution...................................................................................8 pin configuration and function descriptions ..............................9 typical performace characteristics ............................................. 12 theory of operation ...................................................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 10/08 rev. 0 to rev. a changes to the vcom buffer offset parameter, table 1 ............ 7 1/06 revision 0: initial version
adate206 rev. a | page 3 of 16 specifications electrical characteristics v cc = 10.0 v, v ee = ? 5.0 v, t j = 75c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments driver single-ended logic input characteristics (vten, drv_inv) threshold voltage cmos_vdd/2 v voltage range 0 5.5 v bias current ?10 +10 a v in = 0 v, 3.3 v single-ended logic input characteristics (slew0, slew1) threshold voltage cmos_vdd/2 v voltage range 0 5.5 v bias current ?10 +600 (@ 3.3 v) +800 a v in = 0 v, 3.3 v bias current 1 ma v in = 5.5 v differential logic input characteristics (dr_data_n, dr_data_p, dr_en_n, dr_en_p) voltage range ?2.0 +3.5 v differential voltage with lvpecl levels 250 300 mv bias current ?10 +2 +10 a v in = 3.24 v, 3.495 v vih, vil reference inputs input bias current ?10 ?2 +10 a maximum value bias of reference sweep vit reference inputs input bias current ?25 +12 +25 a maximum value bias of reference sweep dc output characteristics logic range, vil, vih, vit ?1.5 +6.5 v amplitude [vh to vl] 8 v output resistance 47.5 52.5 psrr, drive or term mode 10 mv/v v cc , v ee 1% static current limit ?125 110 +125 ma output to ?1.5 v, vh = 6.5 v, vt = 0 v absolute accuracyvih, vil, vit vih offset ?100 +30 +100 mv data = h, vh = 0 v, vl = ?1.5 v, vt = 3 v vih gain error 0.98 1.02 v/v data = h, vh = 0 v to 5 v, vl = ?1.5 v, vt = 3 v vih linearity error ?15 +5 +15 mv data = vh relative to line between 0 v to 5 v; full range of vih = ?1.4 v to +6.5 v vil offset ?100 +30 +100 mv vil gain error 0.98 1.02 v/v data = l, vl = 0 v to 5 v, vh = 6.5 v, vt = 3 v vil linearity error ?15 +5 +15 mv data = vh relative to line between 0 v to 5 v; full range of vih = ?1.4 v to +6.5 v vit offset ?100 +30 +100 mv data = vt, vt = 0 v, vl = 0 v, vh = 3 v vit gain error 0.98 1.02 v/v data = vt, vt = 0 v to 5 v, vl = 0 v, vh = 3 v
adate206 rev. a | page 4 of 16 parameter min typ max unit test conditions/comments vit linearity error ?15 +5 +15 mv data = vh relative to line between 0 v to 5 v; full range of vih = ?1.4 v to +6.5 v offset tempco 80 v/c 65c to 105c driver interaction vh interaction to vl ?2 +2 mv vih = 5.0 v; vil = ?1.5 v, +4.7 v, +4.8 v, +4.9 v vh interaction to vt ?2 +2 mv vih = 3.0 v; vit = ?1.5 v, +2.9 v, +3.1 v, +6.5 v vl interaction to vh ?2 +2 mv vil = 0.0 v; vih = 0.1 v, 0.2 v, 0.3 v, 6.5 v vl interaction to vt ?2 +2 mv vil = 0.0 v; vit = ?1.5 v, ?0.1 v, +0.1 v, +6.5 v vt interaction to vh ?2 +2 mv vit = 1.5 v, vil = ?1.0 v; vih = ?0.8 v, +1.4 v, +1.6 v, +6.5 v vt interaction to vl ?2 +2 mv vit = 1.5 v, vih = 6.0 v; il = ?1.5 v, +1.4 v, +1.6 v, +5.8 v rise/fall times at device under testing (dut) 0.2 v swing: rise/fall time 300 ps terminated 20% to 80%, vih = 400 mv, vil = 0 v, vit = 0 v 0.5 v swing: rise/fall time 350 ps terminated 10% to 90%, vih = 1.0 v, vil = 0 v, vit = 0 v 1 v swing: rise/fall time 500 ps terminated 10% to 90%, vih = 2.0 v, vil = 0 v, vit = 0 v 3 v swing: rise/fall time 650 ps unterminated 10% to 90%, vih = 3.0 v, vil = 0 v, vit = 0 v 3 v swing: rise/fall time 350 450 550 ps terminated 20% to 80%, vih = 3.0 v, vil = 0 v, vit = 0 v using dut comparator 5 v swing: rise/fall time 1.1 ns unterminated 10% to 90%, vih = 5.0 v, vil = 0 v, vit = 0 v minimum pulse width at dut 500 mv swing 1 500 ps terminated, vih = 1.0 v, vil = 0 v, vit = 0 v 1.5 v swing 1 800 ps terminated, vih = 3.0 v, vil = 0 v, vit = 0 v toggle rate @ 3 v 500 mhz unterminated, 50/50 dc measured frequency when amplitude drops 10% dynamic performance, drive (vh and vl) propagation delay time 2 1.4 ns terminated, vih = 3.0 v, vil = 0.0 v, vit = 0.0 v propagation delay tempco 2 2.0 ps/c terminated, vih = 3.0 v, vil = 0.0 v, vit = 0.0 v, 65c to 85c delay matching, edge-to-edge 20 ps delay change vs. pulse width 2 30 ps terminated, vih = 3.0 v, vil = 0.0 v, vit = 0.0 v, 1s period, pulse width = 50 ns to 1 ns delay change vs. duty cycle 2 5 ps terminated, vih = 3.0 v, vil = 0.0 v, vit = 0.0 v, 1 s period; 10%, 50%, and 90% duty cycle
adate206 rev. a | page 5 of 16 parameter min typ max unit test conditions/comments settling time to 15 mv 8 ns terminated, vih = 3 v, vil = 0.0 v, vit = 0.0 v settling time to 4 mv 32 ns terminated, vih = 3 v, vil = 0.0 v, vit = 0.0 v rise and fall time temperature coefficient 500 mv swing 2 ps/c terminated 10% to 90%, vih = 1.0 v, vil = 0.0 v, vit = 0.0 v, 65c to 85c 1 v swing 2 ps/c terminated 10% to 90%, vih = 2.0 v, vil = 0.0 v, vit = 0.0 v, 65c to 85c 3 v swing 2 ps/c unterminated 10% to 90%, vih = 3.0 v, vil = 0.0 v, vit = 0.0 v, 65c to 85c 5 v swing 2 ps/c unterminated 10% to 90%, vih = 5.0 v, vil = 0.0 v, vit = 0.0 v, 65c to 85c overshoot and preshoot 200 mv swing 1 % terminated, vih = 400 mv overshoot and preshoot 1 v swing 1 % terminated, vih = 2 v overshoot and preshoot 3 v swing 2 % unterminated overshoot and preshoot 5 v swing 2 % unterminated dynamic performance, inhibit delay time, active high to inhibit 3 3.1 ns terminated, vih = 3.0 v, vil = ?1.0 v delay time, active low to inhibit 3 2.1 ns vh = 3.0 v, vl = ?1.0 v, terminated 50 delay time, inhibit to active high 3 2.5 ns terminated, vih = 3.0 v, vil = ?1.0 v delay time, inhibit to active low 3 3.9 ns terminated, vih = 3.0 v, vil = ?1.0 v i/o spike 350 mv terminated, vih = 0.0 v, vil = 0.0 v, vit = 0.0 v clamps vcph, vcpl clamp inputs vcph voltage range clampl 6.8 v vcpl voltage range ?1.8 clamph v input bias current ?50 ?2 +50 a maximum value bias of reference sweep = ?1.8 v to +6.8 v absolute accuracy vcph, vcpl vcph offset ?100 +55 +100 mv driver = inh, vcph = 0 v vcph gain error 1 v/v vcph linearity error +10 mv driver = inh, relative to line between 0 v to 4.5 v, vcph = ?1.5 v to +6.5 v, vcpl = ?1.8 v vcpl offset ?100 +55 +100 mv driver = inh, vcpl = 0 v vcpl gain error 1 v/v vcpl linearity error +10 mv driver = inh, relative to line between 0 v to 4.5 v, vcpl = ?1.5 v to +6.5 v, vcph = 6.5 v comparator dc specifications 4 dc input characteristics (voh, vol) bias current ?10 +5 +10 a voh and vol = ?1.5 v to +6.5 v voltage range ?1.5 +6.5 v differential voltage ?8.0 +8.0 v
adate206 rev. a | page 6 of 16 parameter min typ max unit test conditions/comments offset ?15 +15 mv common mode = 0 v gain error 1 % fsr v in = ?1.5 v to +6.5 v linearity error 3 mv v in = ?1.5 v to +6.5 v single-ended logic input characteristics threshold voltage (cllm) cmos_vdd/2 v voltage range 0 5.5 v bias current ?10 +160 +200 a v in = 0 v, 3.3 v bias current 260 a v in = 5.5 v digital output characteristics (voh, vol levels) logic 1 3.1 3.26 3.4 v terminated 50 to 3.3 v logic 0 2.7 2.86 3.1 v terminated 50 to 3.3 v differential levels 350 400 450 mv terminated 50 to 3.3 v comparator ac specifications propagation delay input to output 500 ps v in = 3 v p-p, 2 v/ns propagation delay tempco 1.0 ps/c v in = 3 v p-p, 2 v/ns propagation delay change with respect to pd vs. duty cycle 40 ps v in = 0 v to 3 v, 2 v/ns, driver in vterm, vit = 0 v, period = 10 ns; dc = 1 ns, 5 ns, 9 ns slew rate: 1 v/ns, 2 v/ns, 3 v/ns 30 ps v in = 0 v to 3 v, driver in vterm, vit = 0 v amplitude: 500 mv, 1.0 v, 3.0 v 30 ps v in = 0 v to 500 mv, 0 v to 1 v, 0 v to 3 v, 2 v/ns, driver in vterm, vit = 0 v equivalent input rise time 225 ps v in = 0 v to 1 v, <50 ps, 20% to 80% rise time, driver in vterm = 0 v pulse-width linearity 20 ps v in = 0 v to 3 v, 2 v/ns; pulse width = 3 ns, 4 ns, 5 ns, 10 ns; driver in vterm, vit = 0 v settling time 5.5 ns settling to 8 mv, v in = 0 v to 3 v, driver in vterm, vit = 0 v minimum pulse width 1 ns 2 v terminated, 1 v at the comparator, driver in vterm, vit = 0 v, 1 s period, pulse width = 50 ns to 1 ns hysteresis 6 mv v in = 100 mv, sweep cvl and cvh comparator propagation delay matching, hcomp to lcomp 50 ps hcomp rise to lcomp rise, hcomp fall to lcomp fall load dc specifications single-ended logic input characteristics threshold voltage (lden) cmos_vdd/2 v voltage range 0 5.5 v bias current ?10 +10 a v in = 0 v, 3.3 v input characteristics viol current program range 0.0 3.5 v vdut = ?1.5 v, +6.5 v; iol = 0 ma to 35 ma vioh current program range 0.0 3.5 v vdut = ?1.5 v, +6.5 v; ioh = 0 ma to 35 ma vioh, viol input bias current ?10 +10 a viol = 0 v, 3.5 v; vioh = 0 v, 3.5 v vdut range ?1.5 +6.5 v |vdut ? vcom| > 1.0 v
adate206 rev. a | page 7 of 16 parameter min typ max unit test conditions/comments vdut range ?1.5 +6.5 v vdut ? vcom > 1.0 v; ioh = 0 ma to 35 ma vdut range ?1.5 +6.5 v vcom ? vdut > 1.0 v; iol = 0 ma to 35 ma output characteristics gain 9.5 10 10.5 ma/v slope of line between 5 ma and 30 ma load offset, ioh, iol t ?200 +200 a ioh and iol programmed at 20 mv (200 a) load nonlinearity, ioh, iol t ?50 +50 a relative to a line from 5 ma to 30 ma; iol, ioh from 200 a to 35 ma output current tempco, ioh, iol t 3 a/c measured at ioh, iol = 30 ma vcom buffer (through bridge) vcom buffer offset ?50 +3 +50 mv iol, ioh = 20 ma, vcom = 0 v vcom buffer bias current ?10 +1 +10 a vcom = ?1.5 v to +6.5 v vcom buffer gain 0.99 1 1.01 v/v iol, ioh = 20 ma, vcom = ?1.5 v to +6.5 v vcom buffer linearity error ?10 +1 +10 mv iol, ioh = 20 ma, vcom = ?1.5 v to +6.5 v, relative to a line at 0 v and 5 v dynamic performance propagation delayi max to inhibit 2.3 ns vtt = 2 v, vcom = 4 v/0 v, iol = 20 ma, ioh = 20 ma inhibit to i max 2.3 ns vtt = 2 v, vcom = 4 v/0 v, iol = 20 ma, ioh = 20 ma total function output leakage current ?1.5 +0.28 +1.5 a driver = inh, vdut swept from ?1.5 v to +6.5 v output leakage current, low leakage mode ?200 +10 +200 na driver = inh, vdut swept from ?1.5 v to +6.5 v output capacitance 2 pf power supplies 5 total supply range 15.5 v positive supply, v cc 9.75 10.0 10.25 v negative supply, v ee ?5.25 ?5.0 ?4.75 v positive supply current, v cc 190 210 245 ma load enabled at 20 ma, driver is set to vil = 0 v negative supply current, v ee 240 270 300 ma load enabled at 20 ma, driver is set to vil = 0 v total power dissipation 2.5 3.5 4 w load enabled at 20 ma, driver is set to vil = 0 v positive supply current load disabled, v cc 145 165 200 ma load enabled at 0 ma, driver is set to vil = 0 v negative supply current load disabled, v ee 190 220 250 ma load enabled at 0 ma, driver is set to vil = 0 v total power dissipation 1.8 2.8 3.3 w load enabled at 0 ma, driver is set to vil = 0 v temperature sensor gain factor 10 mv/c five diodes in series 1 1 s period, pulse width = 50 ns to 500 ps, pulse width measured when amplitude drops 10%. 2 measured at 50% of input amp to 50% of output amp. 3 t pd measured from the 50% of enable signal to 50% of output. 4 the low leakage mode of the comparator, controlled by vllm inpu t, reduces the leakage due to the comparator input. the compara tor operates in this mode, but its bandwidth is compromised and is not guaranteed. 5 under no circumstances should the input voltages exceed the supply voltages.
adate206 rev. a | page 8 of 16 absolute maximum ratings table 2. parameter rating maximum current for vcc 245 ma maximum current for vee 300 ma positive supply voltage (vcc to gnd) +10.5 v negative supply voltage (vee to gnd) ?5.5 v operating temperature (junction) +150c storage temperature range ?65c to +150c esd (human body model) 1500 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adate206 rev. a | page 9 of 16 pin configuration and fu nction descriptions 74 gndref_2 73 vioh_2 72 viol_2 69 vit_2 70 d_inv_2 71 gnd 75 vcom_2 68 vil_2 67 vih_2 66 clamph_2 64 gnd 63 cllm_2 62 lden_2 61 vten_2 60 vee 59 vee 58 vcc 57 vcc 56 gnd 55 gnd 54 dr_data_p_2 53 dr_data_p_t_2 52 dr_data_n_t_2 51 dr_data_n_2 65 clampl_2 pin 1 100 gnd 99 vcc 98 vcc 97 gnd 96 gnd/shields 95 dut_1 94 gnd/shields 93 gnd 92 vee 91 cvh_1 90 cvl_1 89 vcc 88 temp 87 vee 86 cvl_2 85 cvh_2 84 vee 83 gnd 82 gnd/shields 81 dut_2 80 gnd/shields 79 gnd 78 vcc 77 vcc 76 gnd 26 dr_en_p_1 27 dr_en_p_t_1 28 1 dr_en_n_t_ 29 dr_en_n_1 30 nc 31 comp_h_p_1 32 comp_h_n_1 33 vee 34 comp_l_p_1 35 comp_l_n_1 36 d gn 37 1 slew 38 d cmos_vd 39 0 slew 40 d gn 41 comp_l_n_2 42 comp_l_p_2 43 vee 44 comp_h_n_2 45 comp_h_p_2 46 nc 47 dr_en_n_2 48 2 dr_en_n_t_ 49 dr_en_p_t_2 50 dr_en_p_2 2 gndref_1 3 vioh_1 4 viol_1 7 vit_1 6 d_inv_1 5 gnd 1 vcom_1 8 vil_1 9 vih_1 10 clampl_1 12 gnd 13 cllm_1 14 lden_1 15 vten_1 16 vee 17 vee 18 vcc 19 vcc 20 gnd 21 gnd 22 dr_data_p_1 23 dr_data_p_t_1 24 dr_data_n_t_1 25 dr_data_n_1 11 clamph_1 adate206 top view (not to scale) 05738-002 figure 2. pin configuration
adate206 rev. a | page 10 of 16 table 3. pin function descriptions pin no. mnemonic description 1 vcom_1 commutation reference voltage. 2 gndref_1 reference gnd for viol, vioh. 3 vioh_1 program voltage for ioh (sink). 4 viol_1 program voltage for iol (source). 5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97, 100 gnd device ground. 6 d_inv_1 driver invert. 7 vit_1 driver term voltage reference. 8 vil_1 driver low voltage reference. 9 vih_1 driver high voltage reference. 10 clampl_1 low clamp. 11 clamph_1 high clamp. 13 cllm_1 comparator low leakage mode. 14 lden_1 determines whether ld respon ds to dr_en_1 or is disabled (see table 4 ). 15 vten_1 low speed control signal. when high, dr_en_1 forces driver output to vit. otherwise, dr_en_1 forces driver to high impedance (see table 4 ). 16, 17, 33, 43, 59, 60, 84, 87, 92 vee negative power supply. 18 19, 57, 58, 77, 78, 89, 98, 99 vcc positive power supply. 22 dr_data_p_1 high speed data inputs. sets high/low state of driver output (see table 4 ). 23 dr_data_p_t_1 termination resistor for hs inputs. opposite end of each 50 termination resistor goes to the appropriate signal. 24 dr_data_n_t_1 termination resistors for hs inputs. opposite end of each 50 termination resistor goes to the appropriate signal. 25 dr_data_n_1 complement of dr_data_p_1. 26 dr_en_p_1 high speed enable inputs. multifunction depending on status of vten_1 and lden_1. causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see table 4 ). 27 dr_en_p_t_1 termination resistor for hs inputs. opposite end of each 50 termination resistor goes to the appropriate signal. 28 dr_en_n_t_1 termination resistor for hs inputs. opposite end of each 50 termination resistor goes to the appropriate signal. 29 dr_en_n_1 complement of dr_en_p_1. 30, 46 nc no connect. 31 comp_h_p_1 high comparator output. 32 comp_h_n_1 complement of comp_h_p_1. 34 comp_l_p_1 low comparator output. 35 comp_l_n_1 complement of comp_l_p_1. 37, 39 slew1, slew0 logic signals controlling driver slew rates for both drivers. 00 codes for maximum slew voltage; 11 codes for minimum slew voltage. 38 cmos_vdd cmos supply (internal 2 = single-ended logic reference). 41 comp_l_n_2 complement of comp_l_p_1. 42 comp_l_p_2 low comparator output. 44 comp_h_n_2 complement of comp_h_p_1. 45 comp_h_p_2 high comparator output.
adate206 rev. a | page 11 of 16 pin no. mnemonic description 47 dr_en_n_2 complement of dr_en_p_2. 48 dr_en_n_t_2 complement of dr_en_p_t_2. 49 dr_en_p_t_2 termination resistor for hs inputs. opposite end of each 50 termination resistor goes to the appropriate signal. 50 dr_en_p_2 high speed enable input. multifunction depending on status of vten_2 and lden_2. causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see table 4 ). 51 dr_data_n_2 complement of dr_data_p_2. 52 dr_data_n_t_2 complement of dr_data_p_t_2. 53 dr_data_p_t_2 termination resistor for hs inputs. opposite end of each 50 termination resistor goes to the appropriate signal. 54 dr_data_p_2 high speed data input. se ts high/low state of driver output (see table 4 ). 61 vten_2 low speed control signal. when high, dr_en_2 forces driver output to vt; otherwise, dr_en_2 forces driver to high impedance (see table 4 ). 62 lden_2 determines whether ld respon ds to dr_en_2 or is disabled (see table 4 ). 63 cllm_2 comp low leakage mode. 65 clampl_2 low clamp. 66 clamph_2 high clamp. 67 vih_2 driver high voltage reference. 68 vil_2 driver low voltage reference. 69 vit_2 driver term voltage reference. 70 d_inv_2 driver invert. 72 viol_2 program voltage for iol (source). 73 vioh_2 program voltage for ioh (sink). 74 gndref_2 reference gnd for viol, vioh. 75 vcom_2 commutation reference voltage. 80, 82, 94, 96 gnd/shields device ground or pin shield. 81 dut_2 output/input pin. 85 cvh_2 window high reference level. 86 cvl_2 window low reference level. 88 temp temperature sense, five diode string, reference to gnd. 90 cvl_1 window low reference level. 91 cvh_1 window high reference level. 95 dut_1 output/input pin.
adate206 rev. a | page 12 of 16 typical performace characteristics 2400 2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 05738-003 200mv/di 0 2 4 6 10 12 14 16 81 8 v 2ns/div vil = 0v termination = 50 ? vih = 5v vih = 3v vih = 1v figure 3. driver large signal response 240 220 200 180 160 140 120 100 80 60 40 20 0 05738-004 20mv/di 0 2 4 6 10 12 14 16 81 8 v 2ns/div vil = 0v termination = 50 ? vih = 500mv vih = 200mv vih = 100mv figure 4. driver small signal response trailing fall edge trailing rise edge 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 05738-005 10ps/di 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 v 2.5ns/div figure 5. driver trailing edge timing error vs. pulse width 5 3 2 1 4 0 ?1 ?3 ?2 ?6 ?4 ?5 ?2 ?1 0 1 3 4 5 6 27 05738-006 linearity error (mv) v dut (v) driver = vih figure 6. driver vih linearity vs. output 6 4 3 2 5 1 0 ?2 ?1 ?5 ?3 ?4 ?2 ?1 0 1 3 4 5 6 27 05738-007 linearity error (mv) v dut (v) driver = vil figure 7. driver vil linearity vs. output 8 4 2 6 0 ?4 ?2 ?8 ?6 ?2 ?1 0 1 3 4 5 6 27 05738-008 linearity error (mv) v dut (v) driver = vterm figure 8. driver vterm linearity vs. output
adate206 rev. a | page 13 of 16 1.0004 1.0003 1.0002 1.0001 1.0000 0.9999 0.9998 0.9997 0.9996 0.9995 05738-009 gain (v/v) 60 70 90 100 80 110 temperature (c) figure 9. driver gain vs. temperature 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 05738-010 offset (mv) 60 70 90 100 80 110 temperature (c) figure 10. driver offset vs. temperature 240 220 200 180 160 140 120 100 80 60 40 20mv/div 20 0 2 4 6 8 10 12 14 16 18 20 05738-011 t base (2ns/div) figure 11. comparator differential output response 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?2 ?1 0 1 3 5 46 27 05738-012 offset (mv) common-mode voltage (v) figure 12. comparator offset vs. common-mode voltage 1050 1100 950 1000 900 850 750 800 700 650 600 550 450 500 350 400 300 250 150 200 100 50 ?50 0 ?100 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 8000 7500 8000 8500 9000 9500 0 05738-016 50mv/di v 500ps/div v in = 0v to 1v <50ps 20% to 80% rise time driver in vterm = 0v figure 13. comparator schmoo at 1 ns rise and fall time 1050 1100 950 1000 900 850 750 800 700 650 600 550 450 500 350 400 300 250 150 200 100 50 ?50 0 ?100 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 8000 7500 8000 8500 9000 9500 0 05738-017 50mv/di v 500ps/div v in = 0v to 1v <50ps 20% to 80% rise time driver in vterm = 0v figure 14. comparator schmoo at 600 ps rise and fall time
adate206 rev. a | page 14 of 16 32.0 27.5 30.0 20.0 22.0 25.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 2.5ps/di 0 ?3.0 12 3456 78910 05738-018 v 1ns/div figure 15. comparator t pd vs. pulse width 40 20 10 30 0 ?10 ?20 i dut (ma) ?30 ?40 ?2 ?1 0 1 3 4 5 6 27 05738-013 v dut (v) v com = 1v ioh = iol = 35ma figure 16. active load commutation region 18 12 10 8 14 16 6 4 2 ?2 0 ?4 0 5 10 20 25 30 15 35 05738-014 linearity error (a) iol (ma) v com = 0v iol = 0v v dut = 2v figure 17. active load linearity vs. ioh 14 8 6 4 10 12 2 0 ?4 ?2 ?6 0 5 10 20 25 30 15 35 05738-015 linearity error (a) iol (ma) v com = 2v ioh = 0v v dut = 0v figure 18. active load linearity vs. iol
adate206 rev. a | page 15 of 16 theory of operation the adate206 has two general classes of logic inputs: differential inputs for controlling functions that generally need to be operated at high speed, and single-ended cmos inputs for setting operating modes or other low speed functions. the differential inputs have a wide common-mode range that allows them to be used with a variety of logic families. the differential inputs can be used single-ended, with one input from each pair of inputs tied to a fixed reference. however, this makes precise timing more difficult to achieve. these differential input pins provide 50 input termination resistors for use as desired. the single-ended inputs have an input range compatible with most logic families and are high impedance to make driving them very easy. the switching threshold for the single-ended inputs is preset to one-half of the voltage at the cmos_vdd pin. table 4. driver and load modes lden (cmos single-ended) vten (cmos single-ended) dr_en (high speed differential) dr_data (high speed differential) driver status load status 0 0 0 x high-z high-z 0 0 1 0 vil high-z 0 0 1 1 vih high-z 0 1 0 x vit high-z 0 1 1 0 vil high-z 0 1 1 1 vih high-z 1 0 0 x high-z on 1 0 1 0 vil high-z 1 0 1 1 vih high-z table 5. comparator low leakage mode cllm (cmos single-ended) typical dut pin bias current 0 1 a 1 10 na table 6. rise/fall time selection 3 v, 10% to 90%, unterminated slew1 slew0 tr/tf (ns) 0 0 0.7 0 1 0.95 1 0 1.4 1 1 2.8 table 7. comparator logic function dut pin voltage output states comp_l_p comp_l_n comp_h_p comp_h_n >cvl >cvh 1 0 1 0 >cvl cvh 0 1 1 0 adate206 rev. a | page 16 of 16 compliant to jedec standards ms-026-aed-hd outline dimensions 0.27 0.22 0.17 1 25 26 49 76 100 75 50 14.00 bsc sq 16.00 bsc sq 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 25 26 50 76 100 75 51 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a seating plane rotated 90 ccw 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 6.50 sq exposed pad bottom view (pins up) figure 19. 100-lead thin quad flat package, exposed pad [tqfp_ep] (sv-100-2) dimensions shown in millimeters ordering guide model temperature range packag e description package option adate206bsv ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-2 ?2006C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05738-0-10/08(a)

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